Machine learning optimizes trapped-ion quantum computing

Reinforcement learning beats state-of-the-art techniques for ion shuttling

An interdisciplinary team of researchers at the Institute for Gravitational Physics and the Institute for Information Processing at Leibniz University Hannover and at QUDORA Technologies GmbH has devised a new scheme to move around ions in certain types of quantum computers. On those trapped-ion quantum computers, it is often necessary to transport the ions between different zones on a chip. This process known as “ion shuttling” usually takes the most time when executing a quantum circuit. Because the quantum bits decohere quickly, it is crucial to make ion shuttling as efficient as possible. A large number of quantum bits and hence large numbers of ions results in a high-dimensional optimization problem. This makes finding optimal solutions extremely hard, and shuttling schemes usually rely on heuristics. The team tackled the ion shuttling problem using reinforcement learning. Their novel method achieves up to a 36% advantage over state-of-the-art techniques and is adaptable to different chip architectures, making it a versatile tool for future, more complex quantum chip architectures.

Paper abstract

Scalable trapped-ion quantum computing is commonly realized with modular chips that feature distinct zones with specific functionalities, such as storage, state preparation, and gate execution. To execute a quantum circuit, the ions must be transported between these zones. This process is called ion shuttling. To achieve reliable computation results, the shuttling process must be optimized. However, as the number of ions increases, this becomes a high-dimensional optimization problem where optimal solutions cannot be computed efficiently. We demonstrate, to the best of our knowledge, the first use of reinforcement learning (RL) for the optimization of ion shuttling. RL is well suited for such scenarios, as it enables learning a strategy through direct interaction with the problem. We show that our RL approach outperforms current state-of-the-art heuristic techniques, yielding a reduction in shuttling operations of up to 36.3%. Furthermore, we show that our method is easily applicable to various chip architectures. Our approach offers a versatile method to study shuttling efficiency during chip design and, therefore, a highly relevant tool for future, more complex architectures.