Master of Time: implementing a timing architecture for a LISA spacecraft using SpaceWire (MSc thesis)

Stellenangebot vom 20. Mai 2019

LISA (Laser Interferometer Space Antenna) is an ambitious space mission currently under development. It aims to listen to gravitational-wave sources which are only audible from space and which promise plenty of exciting new science. The mission consists of three spacecraft forming a triangle with 2.5 million km (~7 times the earth-moon distance) arm length. Laser interferometry will be used to measure the distances between test masses on board the spacecraft with picometer precision to ultimately detect gravitational waves which would slightly change these distances.

Each LISA spacecraft consists of different payload components, like Phasemeters, laser controllers and others. All these components generate scientific and diagnostic data, available as streams of digital data samples. In order to be able to post-process these streams with respect to each other, it is of utter importance to know the exact time each sample was taken. A timing architecture has been proposed that is based on a single master SCET (spacecraft elapsed timer). It will be part of the spacecraft's main OBC (on-board computer) and will provide a timing reference to all other payload components via SpaceWire (an ESA spacecraft communication standard).

We want to set up an experiment to verify the feasibility of this timing architecture and the applicability of SpaceWire in LISA. For that purpose, several FPGA-bases mock-up modules representing payload components as well as the main OBC shall be implemented and connected via SpaceWire connections. The SpaceWire interfaces on the single modules are available as IP cores for the integration on the FPGAs. Furthermore,
dedicated logic shall be allocated on the OBC mock-up to generate the SCET synchronization packages. Likewise, the payload mock-ups shall feature logic for the processing of these packages to achieve synchronization with the SCET in all modules.

A student working on this experiment will mainly work on digital electronics implemented on an FPGA using VHDL. Current hardware targets for the mock-up modules are ZynqBerry development boards by Trenz Electronic. Possible tasks would be:

  • consolidation of ZynqBerry reference design
  • startup of digital infrastructure like Ethernet interfaces etc.
  • integration of the SpaceWire IP core
  • development and integration of synchronization logic
  • development of a testing scheme for the successful synchronization

Naturally, experience with VHDL would be beneficial.

Please contact for further information.

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